JPL Begins Multi‑Month Tests of Radiation‑Hardened AI Chip for Deep‑Space Autonomy

NASA’s Jet Propulsion Laboratory has started laboratory and environmental trials of a palm‑sized, radiation‑hardened multicore processor intended to give deep‑space probes orders‑of‑magnitude more onboard compute for autonomous operations and faster science.

The Jet Propulsion Laboratory has launched a multi‑month test campaign of a next‑generation radiation‑hardened processor designed to bring high‑performance computing to deep‑space missions. The High Performance Spaceflight Computing system places a full multicore system‑on‑a‑chip into a palm‑sized package; JPL engineers marked the start of testing by sending a symbolic “Hello Universe” email. Successful validation would let spacecraft run complex autonomy and sensor processing on board instead of relying on Earth for time‑sensitive decisions, potentially speeding landings and science returns.

The processor is a fault‑tolerant, multicore system‑on‑a‑chip engineered to survive intense electromagnetic radiation, dramatic temperature swings and bombardment by high‑energy particles. NASA describes the design as capable of up to 100× the computing power of current spaceflight hardware; in early laboratory comparisons the team reported roughly 500× the performance of the radiation‑hardened chips now used in spacecraft. Those gains aim to enable advanced onboard algorithms such as artificial‑intelligence decision making and high‑throughput data analysis within the power and size constraints of deep‑space vehicles.

Testing at JPL combines functional evaluations with environmental trials to stress the design under realistic mission conditions. Teams are subjecting the chip to radiation, thermal and shock tests and running mission‑style workloads, including high‑fidelity landing simulations that would normally require heavy, power‑intensive hardware to process large volumes of sensor data. The goal is to demonstrate the chip can handle those compute‑intensive tasks on board a lander or probe during descent, touchdown and science operations.

The work is being executed through a commercial partnership under NASA’s High Performance Spaceflight Computing initiative and is funded as part of the agency’s Game Changing Development program at Langley Research Center. JPL’s formal test campaign began in February and is scheduled to continue for several months while engineers assess both functional performance and environmental resilience against mission requirements.

Validation at this stage highlights concrete integration challenges for spacecraft builders. Teams must prove fault tolerance against single‑event effects, qualify thermal and shock margins for rugged landings, and validate sustained high‑throughput sensor processing for autonomous descent or on‑site science. If the processor continues to meet environmental and functional requirements, it could reshape spacecraft architectures by shifting workloads from specialized, power‑hungry hardware to general‑purpose, AI‑capable processors on board future probes.